View VSC9142_1335057.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

G56054-0, Rev 1.0
SONET/SDH 2.5Gbps Transport Terminating Transceiver
VSC9142.
1.0 Product Description
1.1 Functional Overview
7KH 96& LV D GXDOPRGH 676F$8F 621(76'+ WR SDFNHW$70 IUDPLQJ GHYLFH ,Q WKH 326 SDFNHW RYHU 621(7 PRGH WKH GHYLFH FDQ EH XVHG LQ HTXLSPHQW LQWHUFRQQHFWLQJ ,3333+'/& HTXLSPHQW RYHU SXEOLF RU SULYDWH 621(76'+ QHWZRUNV 6LPLODUO\ LQ WKH $70 RYHU 621(7 $70 PRGH WKLV GHYLFH FDQ EH XVHG LQ HTXLSPHQW LQWHUFRQQHFWLQJ $70 VZLWFKHV )HDWXUHV RI WKH 96& LQFOXGH IXOO LQVHUWLRQH[WUDFWLRQ RI WKH WUDQVSRUW RYHUKHDG ELW HUURU UDWH DQG H[WHQVLYH 621(7SDFNHWFHOO SHUIRUPDQFH PRQLWRULQJ SDFNHWFHOO ILOWHULQJ DQG GLVFDUGLQJ IXQFWLRQDOLWLHV -7$* 7$3 FRQWUROOHU DQG DQ ELW &38 LQWHUIDFH ZLWK HLJKW JHQHUDO SXUSRVH ,2 SRUWV :KHQ XVHG LQ FRQMXQFWLRQ ZLWK D KLJKVSHHG PX[GHPX[ WUDQVFHLYHU WKLV GHYLFH SURYLGHV D FRPSOHWH SK\VLFDO OD\HU VROXWLRQ IRU SDFNHW$70 RYHU 621(76'+ /$36 ,78 &20 DQG FHUWDLQ (WKHUQHW RYHU 621(76'+ DSSOLFDWLRQV DW WKH 676670 OLQH UDWH ,Q DGGLWLRQ WKLV GHYLFH SURYLGHV D ELW LQWHUIDFH IRU KLJKHU EDQGZLGWK DSSOLFDWLRQV DW 676670 OLQH UDWHV 7KH
96& LQWHJUDWHV WKH IROORZLQJ PDMRU IXQFWLRQDO EORFNV LOOXVWUDWHG LQ )LJXUH 6HULDO RU ELW /LQH6LGH ,QWHUIDFH ELW 3DFNHW8723,$ 'URS6LGH ,QWHUIDFH 3DFNHW$70 0DSSLQJ'HPDSSLQJ 621(76'+ 6HFWLRQ /LQH DQG 3DWK 63(9& 2YHUKHDG 3URFHVVLQJ 7UDQVSRUW 2YHUKHDG ,QVHUWLRQ([WUDFWLRQ 621(76'+ 6HFWLRQ DQG 3DWK 7UDFH %XIIHUV *HQHULF %LW 0LFURSURFHVVRU ,QWHUIDFH %LW (UURU 5DWH 0RQLWRU -7$* 7HVW $FFHVV 3RUW
1.0 Product Description
Page 1.
STS-48c Physical Layer Packet/ATM Over SONET/SDH Device
TLPRTY4+/TLOUT[3..0]+/TLCLK4O+/TLCLK4+/TLOUTSER+/TLCLKSER+/CMUREFCLK+/CMUFILTER+/CMULOCKDET CMUREFDET CMUREFSEL[1..0] LOOPTIMING CLKRSTEN RLINSER+/RLINSERMID CRUREFCLK+/CRUFILTER+/CRULOCKDET CRUREFDET CRUREFSEL[1..0] CRUREFOUTSEL CRURECCLK+/RLPRTY4+/RLIN4[3..0]+/RLCLK4+/DMX PHY CRU + DMX Section Termination RSOP Line Termination RLOP Path Termination RPOP Packet/ATM Demapping RPP/RACP PIF/UIF PHY Section Trace Buffer SSTB Path Trace Buffer SPTB Section Generation CMU + MUX TSOP Line Generation TLOP Path Generation TPOP Packet/ATM Mapping TPP/TACP MUX Transport Overhead Insertion TOAP JTAG
System Layer Interface POSPHY-3 Packet Interface / UTOPIA-3 Cell Interface
TFCLK TFCLKO TENB DTPA TSOP TPRTY TDAT[31..0] TMOD[1..0] TEOP TERR RFCLK RFCLKO RENB RVAL RSOP RPRTY RDAT[31..0] RMOD[1..0] REOP RERR
Transport Overhead Extraction ROAP
BERM
CPU
GPIO[7..0] PMTICK
G56054, Rev 1.0
VSC9142
Figure1.1. VSC9142 Functional Block Diagram
RXRCLK TXRCLK LOPC
RTOHCLK RTOHVALID RTOHFP RTOH[3..0]
RSPCLK1 RSPVALID1 RSPDAT1
RSPFP
RSPCLK2 RSPVALID2 RSPDAT2
LCD-P RXTS
D[7..0] A[8..0] ALE CSB WRB RDB RSTB INTB
LOS LOF
Page 2
1.0 Product Description.
TLSYNCLDVS+/TLSYNCTTL PHY4BITSEL
TTOHCLK TTOHREN RTOHFP TTOHEN TTOH[3..0]
TSPCLK1 TSPFP1 TSPREN1 TSPDAT1
TSPCLK2 TSPFP2 TSPREN2 TSPDAT2
TCK OE TRSTB TMS TDI TDO
TXST
G56054-0, Rev 1.0
SONET/SDH 2.5Gbps Transport Terminating Transceiver
VSC9142.
1.2 VSC9142 Functional Blocks
7KH 96& LV SDUWLWLRQHG LQWR WKH IXQFWLRQDO EORFNV VKRZQ LQ )LJXUH 7KH EXOOHWV EHORZ GHILQH WKH HVVHQWLDO IXQFWLRQ RI WKH GDWD WUDQVPLW DQG UHFHLYH EORFNV 7KH VHFWLRQV IROORZLQJ WKH EXOOHWV VXPPDUL]H WKH NH\ IHDWXUHV RI HDFK IXQFWLRQDO EORFN LQ )LJXUH 3K\VLFDO /LQH 6LGH ,QWHUIDFH 3+< LV WKH LQWHUIDFH EHWZHHQ WKH OLQH VLGH DQG WKH 96&*V 621(76'+ RYHUKHDG DQG SD\ORDG SURFHVVLQJ 7KH 3+< SHUIRUPV FORFN DQG GDWD UHFRYHU\ RQ UHFHLYHG GDWD LQ DGGLWLRQ WR GHVHULDOL]DWLRQ 6HULDOL]DWLRQ DQG FORFN PXOWLSOLFDWLRQ LV SHUIRUPHG RQ WKH WUDQVPLW GDWD $Q RSWLRQDO ELW LQWHUIDFH IRU 676 XVH LV SURYLGHG LQ ERWK WKH WUDQVPLW DQG UHFHLYH GLUHFWLRQ 6HFWLRQ RYHUKHDG SURFHVVLQJ 5623 UHVSRQVLELOLWLHV LQ WKH UHFHLYH 5[ IORZ DUH IUDPH V\QFKURQL]DWLRQ DQG GHVFUDPEOLQJ SOXV 6HFWLRQ DODUPV DQG HUURU PRQLWRULQJ 7UDQVPLW 7[ 6HFWLRQ RYHUKHDG SURFHVVLQJ 7623 RSHUDWLRQV LQFOXGH IUDPH SDWWHUQ JHQHUDWLRQ ZLWK VFUDPEOLQJ DQG DODUP DQG 6HFWLRQ HUURU LQVHUWLRQ 7KH 5[ IORZ SRUWLRQ RI WKH /LQH RYHUKHDG SURFHVVLQJ EORFNV 5/237/23 KDQGOHV /LQH DODUP DQG HUURU PRQLWRULQJ DXWRPDWLF SURWHFWLRQ VZLWFKLQJ DQG V\QFKURQL]DWLRQ VWDWXV H[WUDFWLRQ RQ WKH 5[ IORZ /LQH RYHUKHDG SURFHVVLQJ LQ WKH 7[ IORZ LQFOXGH /LQH DODUP LQVHUWLRQ HUURU FRGH LQVHUWLRQ DXWRPDWLF SURWHFWLRQ VZLWFKLQJ LQVHUWLRQ DQG V\QFKURQL]DWLRQ VWDWXV LQVHUWLRQ 5[ IORZ IXQFWLRQV LQ WKH 3DWK RYHUKHDG SURFHVVLQJ EORFNV 53237323 LQFOXGH SRLQWHU LQWHUSUHWDWLRQ 3DWK RYHUKHDG H[WUDFWLRQ DQG PRQLWRULQJ 3DWK DODUPV 7[ IXQFWLRQV IRU 3DWK RYHUKHDG SURFHVVLQJ DUH SRLQWHU JHQHUDWLRQ HUURU FRGH % LQVHUWLRQ DQG VWDWXV EDFNUHSRUWLQJ 3DFNHW SURFHVVLQJ LV KDQGOHG E\ WKH 533733 EORFNV ZKLFK DOVR FRQWDLQ WKH 5$&37$&3 $70 &HOO SURFHVVLQJ EORFNV GHVFULEHG QH[W 3DFNHW SURFHVVLQJ LQFOXGHV 333+'/& IUDPLQJ DQG GHIUDPLQJ ZKHQ WKH 96& LV XVHG LQ 3DFNHWRYHU 621(76'+ DSSOLFDWLRQV ,Q WKH 5[ SDWK WKLV LQFOXGHV +'/& IUDPH ERXQGDU\ DOLJQPHQW GHFRPSUHVVLRQ RI WKH 333 2FWHW6WXIILQJ SURFHGXUH GHWHFWLRQ RI VKRUWORQJ SDFNHWV )&6 FKHFNLQJ DQG DERUW VHTXHQFH GHWHFWLRQ 7[ IXQFWLRQV DUH 333 SDFNHW HQFDSVXODWLRQ 333 RFWHW VWXIILQJ JHQHUDWLRQ RI +'/& IUDPHV )&6 JHQHUDWLRQ DQG VFUDPEOLQJ 9DULRXV GLDJQRVWLF DQG SHUIRUPDQFH PRQLWRULQJ IHDWXUHV DUH DOVR SURYLGHG LQ WKHVH EORFNV

4.0 Electrical & Mechanical Data
Page 3.
G56054, Rev 1.0
STS-48c Physical Layer Packet/ATM Over SONET/SDH Device
VSC9142
7KH $70 FHOO SURFHVVLQJ EORFNV 5$&37$&3 SHUIRUP $70 FHOO PDSSLQJ DQG GHPDSSLQJ IRU $70RYHU621(76'+ DSSOLFDWLRQV 5[ IORZ IXQFWLRQV LQFOXGH $70 FHOO ERXQGDU\ DOLJQPHQW FHOO GHOLQHDWLRQ LGOHXQDVVLJQHG FHOO ILOWHULQJ VLQJOH ELW HUURU FRUUHFWLRQ LQ FHOO KHDGHUV FHOO SD\ORDG GHVFUDPEOLQJ DQG SHUIRUPDQFH PRQLWRULQJ 7[ IORZ IXQFWLRQV LQFOXGH +(& ILHOG JHQHUDWLRQ IRU $70 FHOO KHDGHUV FHOO UDWH DGDSWDWLRQ XVLQJ LGOHXQDVVLJQHG FHOOV DQG FHOO SD\ORDG VFUDPEOLQJ 7KH UHFHLYHWUDQVPLW ),)2V 5[ ),)27[ ),)2 SURYLGH FORFN GRPDLQ V\QFKURQL]DWLRQ DQG EXIIHULQJ EHWZHHQ WKH 621(76'+ WUDQVPLVVLRQ SDWK DQG WKH GURSVLGH $70SDFNHW ),)2 LQWHUIDFH ),)2 RYHUUXQXQGHUUXQ FRQGLWLRQV DUH GHWHFWHG DQG SURJUDPPDEOH IXOOHPSW\ IODJV DUH SURYLGHG 7KH RYHUKHDG DFFHVV SRUW 52$372$3 EORFNV HQDEOH H[WUDFWLRQ DQG LQVHUWLRQ RI WUDQVSRUW RYHUKHDG RFWHWV IRU 621(76'+ IUDPHV 7KH 621(76'+ 6HFWLRQ3DWK WUDFH EXIIHUV 667%637% KDQGOH H[WUDFWLRQ DQG LQVHUWLRQ RI WUDFH PHVVDJHV 7KH 5[ VLGH H[WUDFWV DQG FRPSDUHV UHFHLYHG PHVVDJHV ZLWK H[SHFWHG PHVVDJHV DQG SHUIRUPV SHUVLVWHQF\ FKHFNV 7KH 7[ VLGH LQVHUWV WUDFH PHVVDJHV 7KH 3263+< /HYHO 3DFNHW ,QWHUIDFH8723,$ OLNH $70 &HOO ,QWHUIDFH 3,)8,) EORFN SURYLGHV D SK\VLFDO GURSVLGH XVHULQWHUIDFH EHWZHHQ D SDFNHW$70 QHWZRUN DQG WKH 621(76'+ IORZV LQ WKH 96& GHYLFH 7KH SULPDU\ H[WHUQDO LQWHUIDFHV IRU WKH 3,)8,) EORFN DUH WZR ELW EXVVHV RQH WR WUDQVPLW DQG RQH WR UHFHLYH GDWD 7KH ELW HUURU UDWH PRQLWRU %(50 EORFN SURYLGHV RYHUDOO SHUIRUPDQFH PRQLWRULQJ IRU WKH OLQN PHDVXULQJ %(5V GRZQ WR

7KH -7$* WHVW DFFHVV SRUW -7$* 7$3 HQDEOHV H[WHUQDO ERXQGDU\ VFDQ FRPSOLDQW ZLWK WKH ,((( 6WDQGDUG 7HVW 3RUW DQG %RXQGDU\ 6FDQ $UFKLWHFWXUH VWDQGDUG 7KLV JHQHULF PLFURSURFHVVRU LQWHUIDFH &38 IDFLOLWDWHV DOO GHYLFH FRQILJXUDWLRQ VWDWXV DQG SHUIRUPDQFH LQIRUPDWLRQ H[WUDFWLRQ DQG WHVWPRGH RSHUDWLRQV
1.2.1
Transmit Path Processing
3K\VLFDO /LQH 6LGH ,QWHUIDFH 3+< 6HOHFWDEOH UHIHUHQFH IUHTXHQF\ IRU WKH FORFN PXOWLSOLFDWLRQ XQLW 5HIHUHQFH DQG ORFN GHWHFW VLJQDOV IRU WKH FORFN PXOWLSOLFDWLRQ XQLW
Page 4
1.0 Product Description.
G56054-0, Rev 1.0
SONET/SDH 2.5Gbps Transport Terminating Transceiver
VSC9142.
/RRSWLPLQJ DELOLW\ WR ORFN WKH WUDQVPLW FORFN WR WKH UHFRYHUHG OLQH FORFN )DFLOLW\ ORRSEDFN FDSDELOLW\ IRU VSHFLDO DSSOLFDWLRQ RU WHVW SXUSRVHV ELW LQWHUIDFH ZLWK SURJUDPPDEOH SDULW\ ELW HYHQ RU RGG IRU RXWJRLQJ GDWD DQG V\QFKURQL]DWLRQ SLQ 7/6<1& IRU 676670 DSSOLFDWLRQV 3URJUDPPDEOH UHIHUHQFH FORFN RXWSXW N+] 0+] 0+] RU 0+] GHULYHG IURP WKH WUDQVPLW OLQH VLGH FORFN HLWKHU WKH FORFN PXOWLSOLHU FORFN WKH ELW WUDQVPLW OLQH FORFN
621(76'+ 6HFWLRQ 2YHUKHDG *HQHUDWLRQ 7623 6XSSRUWV LQVHUWLRQ RI /LQH $ODUP ,QGLFDWLRQ 6LJQDO $,6/ LH DOO V LQ WKH OLQHVLGH WUDQVPLW GDWD VWUHDP H[FHSW IRU 6HFWLRQ RYHUKHDG $,6/ LQVHUWLRQ FDQ EH DXWRPDWLFDOO\ WULJJHUHG E\ DFWLYLW\ RQ WKH VSHFLDO SXUSRVH VHULDO LQWHUIDFHV &RPSXWHV DQG LQVHUWV WKH 6HFWLRQ %,3 FRGH LQ % RFWHWV RI WUDQVPLWWHG IUDPHV LQVHUWLRQ RI % HUURUV FDQ EH IRUFHG IRU GLDJQRVWLFV SXUSRVHV *HQHUDWHV DQG LQVHUWV $ $ IUDPLQJ RFWHWV LQ WUDQVPLWWHG IUDPHV LQVHUWLRQ RI IUDPLQJ ELW HUURUV FDQ EH IRUFHG IRU GLDJQRVWLFV SXUSRVHV - RFWHW VXSSRUWV ERWK 621(7 DQG 6'+ IRUPDWV RU FDQ EH SURJUDPPHG WR D IL[HG YDOXH FRPSDWLEOH ZLWK ROGHU HTXLSPHQW XVLQJ & LGHQWLILFDWLRQ RFWHWV = JURZWK RFWHWV VXSSRUWV ERWK 621(7 DQG 6'+ IRUPDWV RU FDQ EH SURJUDPPHG WR FDUU\ & LGHQWLILFDWLRQ RFWHWV IRU FRPSDWLELOLW\ ZLWK ROGHU HTXLSPHQW 2SWLRQDOO\ VFUDPEOHV WKH RXWJRLQJ GDWD VWUHDP ZLWK D IUDPHV\QFKURQRXV VFUDPEOHU RI D VHTXHQFH OHQJWK RI DQG D JHQHUDWLQJ SRO\QRPLDO RI [ [

6XSSRUWV IRUFHG LQVHUWLRQ RI DOO V /26 LQ WKH RXWJRLQJ GDWD VWUHDP DIWHU VFUDPEOLQJ IRU GLDJQRVWLF SXUSRVHV (QDEOHV RFWHWV SUHVHQW DW WKH VSHFLDO SXUSRVH LQSXW SRUWV LQ WKH 72$3 EORFN WR EH LQVHUWHG LQWR WKH '' ( ) DQG - RFWHWV RI WKH RXWJRLQJ 6HFWLRQ RYHUKHDG (QDEOHV DOO UHVHUYHG 6HFWLRQ RYHUKHDG RFWHWV LH IRU IXWXUH QDWLRQDO RU LQWHUQDWLRQDO VWDQGDUGV WR EH ZULWWHQ DV [
621(76'+ 6HFWLRQ3DWK 7UDFH %XIIHUV 667%637% 7UDQVPLW )XQFWLRQV
4.0 Electrical & Mechanical Data Page 5.
G56054, Rev 1.0
STS-48c Physical Layer Packet/ATM Over SONET/SDH Device
VSC9142
6WRUH IUDPH DQG LQVHUW SURJUDPPDEOH WUDFH PHVVDJHV LQWR WUDQVPLW VWUHDP 6XSSRUWV WKUHH GLIIHUHQW 6HFWLRQ3DWK WUDFH PHVVDJH IRUPDWV WUDQVSRUWHG LQ WKH - RFWHW LQ ERWK WKH WUDQVPLW DQG UHFHLYH GLUHFWLRQV LH VLQJOH RFWHW 621(7 PHVVDJHV RFWHW 6'+ PHVVDJHV RU RFWHW 621(7 &//, PHVVDJHV &KHFNV UHFHLYHG 6HFWLRQ3DWK WUDFH PHVVDJHV IRU SHUVLVWHQF\ DQG LVVXHV D PLVPDWFK DODUP LI UHTXLUHG
621(76'+ /LQH 2YHUKHDG *HQHUDWLRQ 7/23 *HQHUDWHV DQG LQVHUWV SURJUDPPDEOH . . $XWRPDWLF 3URWHFWLRQ 6ZLWFKLQJ $36 RFWHWV LQ WKH RXWJRLQJ GDWD VWUHDP *HQHUDWHV DQG LQVHUWV /LQH 5HPRWH 'HIHFW ,QGLFDWLRQ 5',/ LQ WKH RXWJRLQJ GDWD VWUHDP RQ GHWHFWLRQ RI /26 /2) RU $,6/ DODUPV LQ WKH UHFHLYH VWUHDP &DOFXODWHV DQG LQVHUWV /LQH %,3 FRGH LQ RXWJRLQJ % RFWHWV RI WKH FXUUHQW IUDPH LQVHUWLRQ RI % HUURUV FDQ EH IRUFHG IRU GLDJQRVWLFV SXUSRVHV (QDEOHV WKH QXPEHU RI /LQH %,3 HUURUV GHWHFWHG LQ WKH 5HFHLYH /LQH 2YHUKHDG 3URFHVVRU 5/23 WR EH EDFNUHSRUWHG YLD /LQH 5(, LQ WKH 0 RFWHW XS WR HUURUV FDQ EH EDFNUHSRUWHG SHU IUDPH LQ LQGLYLGXDO PRGH 6XSSRUWV LQGLYLGXDO DQG EORFNPRGH EDFNUHSRUWLQJ YLD WKH 0 RFWHW LQVHUWLRQ RI 0 HUURUV FDQ EH IRUFHG IRU GLDJQRVWLFV SXUSRVHV 3URYLGHV IRU LQVHUWLRQ RI D SURJUDPPDEOH 6\QFKURQL]DWLRQ 6WDWXV 66 YDOXH LQ WKH 6 RFWHW ,QVHUWV RFWHWV SUHVHQW DW WKH VSHFLDO SXUSRVH SRUWV RI WKH 7UDQVPLW 2YHUKHDG $FFHVV 3RUW 72$3 LQWR WKH '' ( 6 . DQG . RFWHWV RI WKH RXWJRLQJ /LQH RYHUKHDG (QDEOHV DOO UHVHUYHG /LQH RYHUKHDG RFWHWV LH IRU IXWXUH QDWLRQDO RU LQWHUQDWLRQDO VWDQGDUGV WR EH RYHUZULWWHQ DV [ + + DQG + RFWHWV IURP WKH 7UDQVPLW 2YHUKHDG $FFHVV 3RUW 72$3 FDQ EH LQVHUWHG LQWR WKH + + DQG + RYHUKHDG RFWHWV RU DSSOLHG DV DQ HUURU PDVN WR WKH + + DQG + RYHUKHDG RFWHWV

621(76'+ 2YHUKHDG ,QVHUWLRQ 3RUW 72$3
Page 6
1.0 Product Description.
G56054-0, Rev 1.0
SONET/SDH 2.5Gbps Transport Terminating Transceiver
VSC9142.
3URYLGHV WZR LGHQWLFDO LQGHSHQGHQW VSHFLDO SXUSRVH SRUWV WR HQDEOH LQVHUWLRQ RI VSHFLDO SXUSRVH RFWHWV DQG FHUWDLQ 621(76'+ DODUPV VSHFLILF WR $XWRPDWLF 3URWHFWLRQ 6ZLWFKLQJ $36 LQWR WKH WUDQVSRUW RYHUKHDG (QDEOHV VHOHFWLYH LQVHUWLRQ RI DFTXLUHG WUDQVSRUW RYHUKHDG RFWHWV LQWR FRUUHVSRQGLQJ WUDQVPLWWHG RYHUKHDG RFWHWV RI WKH 621(76'+ IUDPH YLD WKH QLEEOH LQSXW SRUW 772+>@
621(76'+ 3DWK 2YHUKHDG *HQHUDWLRQ 7323 + + SRLQWHU RFWHWV FDQ EH SURJUDPPHG WR VXSSRUW 621(7 RU 6'+ 3RLQWHU GLDJQRVWLF IXQFWLRQV DUH SURYLGHG DQG WKH UHPDLQLQJ + + RFWHWV DUH SURJUDPPDEOH 3DWK %,3 LV FRPSXWHG DQG LQVHUWHG LQ WKH % RFWHW % HUURUV FDQ EH LQVHUWHG IRU GLDJQRVWLFV 7KH QXPEHU RI 3DWK %,3 HUURUV GHWHFWHG LQ WKH 5HFHLYH 3DWK 2YHUKHDG 3URFHVVRU 5323 LV EDFNUHSRUWHG DV 3DWK 5HPRWH (UURU ,QGLFDWLRQV 5(,3 IRU LQVHUWLRQ LQ * RFWHWV VXSSRUWV ERWK LQGLYLGXDO DQG EORFNPRGH DFFXPXODWLRQ 3DWK 5HPRWH 'HIHFW ,QGLFDWLRQV 5',3 LQVHUWLRQ LV RSWLRQDOO\ HQDEOHG RU GLVDEOHG IRU WKH IROORZLQJ DODUPV /26 /2) $,6/ $,63 /233 7,03 81(43 /&'3 DQG 3/03 &XUUHQW DQG SUHYLRXV 5',3 IRUPDWV DUH VXSSRUWHG 3URJUDPPDEOH 3DWK 6LJQDO /DEHO & DQG 3DWK WUDFH - RFWHWV 3URJUDPPDEOH ) + = = DQG = RFWHWV

3DFNHW 3URFHVVLQJ DQG 0RQLWRULQJ 733 3URJUDPPDEOH LQVHUWLRQ RI +'/& )ODJ 6HTXHQFH RFWHW 3URJUDPPDEOH YDOXH IRU PLQLPXP )ODJ 6HTXHQFH RFWHWV WR VHSDUDWH +'/& IUDPHV +'/& $GGUHVV&RQWUROFRPSUHVVLRQ LQVHUWLRQ FRQWURO PHFKDQLVP 3URJUDPPDEOH $GGUHVV ILHOG LQVHUWLRQ DIWHU VWDUW RI )ODJ 6HTXHQFH 3URJUDPPDEOH &RQWURO ILHOG LQVHUWLRQ DIWHU VWDUW RI $GGUHVV ILHOG
4.0 Electrical & Mechanical Data
Page 7.
G56054, Rev 1.0
STS-48c Physical Layer Packet/ATM Over SONET/SDH Device
VSC9142
7KH )UDPH &KHFN 6HTXHQFH )&6 FDQ EH JHQHUDWHG XVLQJ WZR PHWKRGV 8VLQJ WKH ELW &5&&&,77 JHQHUDWLQJ SRO\QRPLDO [ [ [ 8VLQJ WKH ELW &5& JHQHUDWLQJ SRO\QRPLDO [[ [ [ [ [ [ [ [ [ [ [ [ [

2FWHW 6WXIILQJ RU HVFDSLQJ FDQ EH DSSOLHG DIWHU )&6 JHQHUDWLRQ DQG SDUWLDO VFUDPEOLQJ LI HQDEOHG 7KH &RQWURO (VFDSH RFWHW DQG 2FWHW 6WXIILQJ 0DVN DUH SURJUDPPDEOH 7KH $V\F&RQWURO&KDUDFWHU0DS $&&0 FDQ DFFRPPRGDWH D PD[LPXP RI ILYH RFWHW YDOXHV DQG HDFK YDOXH FDQ EH LQGLYLGXDOO\ HQDEOHG RU GLVDEOHG 7UDQVPLWWHG GDWD LV VFUDPEOHG XVLQJ D VHOIV\QFKURQL]LQJ VFUDPEOHU 666 SRO\QRPLDO [ )XOO DQGRU SDUWLDO VFUDPEOLQJ FDQ EH LQGHSHQGHQWO\ HQDEOHG RU GLVDEOHG
7KH LQVHUWHG 333 3URWRFRO ILHOG FDQ EH H[WUDFWHG IURP WKH 7[ ),)2 RU LQWHUQDOO\ JHQHUDWHG ZLWK D SURJUDPPDEOH VL]H DQG YDOXH 7KH 7[ ),)2 LV SURJUDPPDEOH RYHU D UDQJH IURP WR ZRUGV RU XS WR RFWHWV RI GDWD $OO YDOLG SDFNHW RFWHWV VWRUHG LQ WKH 7[ ),)2 DUH UHDG RXW DQG PDSSHG WR 333 3URWRFRO,QIRUPDWLRQ ILHOGV RI JHQHUDWHG 333+'/& IUDPHV 6XSSRUWV SDFNHW DQG ZRUGEDVHG 7[ 3,)8,) WUDQVIHU PRGHV 7KH 7;)B(55 VLJQDO HQDEOHV HUURUV WR EH LQVHUWHG LQWR WKH )&6 RU WKH WUDQVPLWWHG +'/& IUDPH WR EH DERUWHG 7UDQVPLWWHG $GGUHVV &RQWURO RU 3URWRFRO ILHOGV FDQ EH ;25HG ZLWK D SURJUDPPDEOH PDVN YDOXH YLD WKH &38 LQWHUIDFH IRU GLDJQRVWLF SXUSRVHV ELW SHUIRUPDQFH PRQLWRULQJ FRXQWHUV FDQ EH SURJUDPPHG WR REVHUYH 2FWHWV UHDG IURP WKH 7[ ),)2 *RRG +'/& IUDPHV WUDQVPLWWHG LH QRQDERUWHG QRQ)&6 HUURUHG $ERUWHG +'/& IUDPHV WUDQVPLWWHG )&6 (UURUHG +'/& IUDPHV WUDQVPLWWHG /RQJ RU VKRUW SDFNHWV UHDG IURP WKH 7[ ),)2 (PSW\ +'/& IUDPHV WUDQVPLWWHG 2FWHWV EHIRUH RU DIWHU RFWHWVWXIILQJ H[FOXGLQJ $ERUW VHTXHQFHV

$70 &HOO 0DSSLQJ 7$&3
Page 8
1.0 Product Description.
G56054-0, Rev 1.0
SONET/SDH 2.5Gbps Transport Terminating Transceiver
VSC9142.
$70 FHOOV DUH PDSSHG WR 621(7 676F 63(V RU 6'+ 670 $8FV 3URJUDPPDEOH LGOHXQDVVLJQHG FHOOV DUH LQVHUWHG LQWR WKH FHOO VWUHDP 2SWLRQDO VFUDPEOLQJ RI WKH RFWHW LQIRUPDWLRQ ILHOG XVLQJ WKH VHOIV\QFKURQL]LQJ VFUDPEOLQJ SRO\QRPLDO [
+(& JHQHUDWRU FDUULHV RXW &5& FDOFXODWLRQV RYHU WKH ILUVW IRXU KHDGHU RFWHWV XVLQJ WKH JHQHUDWLQJ SRO\QRPLDO [ [ [ DQG WKH FRVHW SRO\QRPLDO [ [ [ FDQ EH DGGHG WR WKH UHVXOW 7KH +(& FDQ WKHQ EH RSWLRQDOO\ LQVHUWHG LQWR WKH ILIWK RFWHW RI FHOO KHDGHUV DV WKH\ DUH UHDG IURP WKH 7[ ),)2

7[ ),)2 DFFRPPRGDWHV XS WR HLJKW $70 FHOOV
8723,$/HYHO 3263+< &HOO3DFNHW 7UDQVPLW ,QWHUIDFH 3,)8,) 6WDQGDUGVFRPSOLDQW 326 SDFNHW RYHU 621(76'+ LQWHUIDFH 3URJUDPPDEOH SDULW\ ELW HYHQ RU RGG FKHFNLQJ ,QWHUIDFH VXSSRUWV ERWK ZRUG DQG SDFNHWFHOOOHYHO WUDQVIHU PRGHV 6LQJOH 3+< 8723,$ OLNH LQWHUIDFH IRU $70 DSSOLFDWLRQV 3URJUDPPDEOH GHFRGHUHVSRQVH WLPH IRU IORZ FRQWURO IODJV '73$ VLJQDO RXWSXW WR LQGLFDWH OHYHO RI WKH 7[ ),)2 ZRUG FRXQW EDVHG RQ SURJUDPPDEOH KLJK DQG ORZ ZDWHU PDUNV 7[ ),)2 UHVHW RU IOXVK YLD WKH &38 LQWHUIDFH
1.2.2
Receive Path Processing
3K\VLFDO /LQH 6LGH ,QWHUIDFH 3+< 6HOHFWDEOH UHIHUHQFH IUHTXHQF\ IRU WKH FORFN UHFRYHU\ XQLW 5HIHUHQFH DQG ORFN GHWHFW VLJQDOV IRU WKH FORFN UHFRYHU\ XQLW (TXLSPHQW ORRSEDFN FDSDELOLW\ IRU VSHFLDO DSSOLFDWLRQ RU WHVW SXUSRVHV ELW LQWHUIDFH ZLWK SURJUDPPDEOH SDULW\ ELW HYHQ RU RGG FKHFNLQJ
4.0 Electrical & Mechanical Data
Page 9.
G56054, Rev 1.0
STS-48c Physical Layer Packet/ATM Over SONET/SDH Device
VSC9142
3URJUDPPDEOH UHIHUHQFH FORFN RXWSXW N+] 0+] 0+] RU 0+] GHULYHG IURP WKH UHFHLYH OLQH VLGH FORFN HLWKHU WKH UHFRYHUHG VHULDO OLQH FORFN RU WKH ELW UHFHLYH FORFN 'HGLFDWHG LQSXW IRU /RVV RI 2SWLFDO &DUULHU /23& DODUP PRQLWRULQJ
621(76'+ 6HFWLRQ 2YHUKHDG 7HUPLQDWLRQ 5623 )UDPH DOLJQPHQW YLD $$ IUDPH SDWWHUQ UHFRJQLWLRQ LQ LQFRPLQJ GDWD VWUHDP 6XSSRUWV RU ELW $$ IUDPLQJ SDWWHUQV 2XW 2I )UDPH 22) DQG /RVV 2I )UDPH /2) DODUP FRQGLWLRQ GHWHFWLRQ ,VVXHV DODUPV IRU /RVV 2I )UDPH /2) FRQGLWLRQ EDVHG RQ SURJUDPPDEOH PRQLWRULQJ RI 22) FRQGLWLRQ 2SWLRQDOO\ GHVFUDPEOHV WKH LQFRPLQJ GDWD VWUHDP ZLWK D JHQHUDWLQJ SRO\QRPLDO RI [ [ DQG D VHTXHQFH OHQJWK RI

'HWHFWV DQG DFFXPXODWHV 6HFWLRQ %,3 HUURUV IURP WKH % RFWHW RI UHFHLYHG IUDPHV VXSSRUWV ERWK LQGLYLGXDO DQG EORFNPRGH DFFXPXODWLRQ 0RQLWRUV IRU DEVHQFH RI WUDQVLWLRQV RU DOO]HUR SDWWHUQ LQ WKH LQFRPLQJ GDWD VWUHDP SULRU WR GHVFUDPEOLQJ 3URYLGHV SURJUDPPDEOH GHWHFWLRQ DQG WHUPLQDWLRQ FULWHULD IRU /RVV 2I 6LJQDO /26 FRQGLWLRQ 6XSSRUWV LQVHUWLRQ RI /LQH $ODUP ,QGLFDWLRQ 6LJQDO $,6/ LH DOO V LQ WKH OLQH VLGH UHFHLYH GDWD VWUHDP H[FHSW IRU 6HFWLRQ RYHUKHDG $,6/ LQVHUWLRQ FDQ EH DXWRPDWLFDOO\ WULJJHUHG RQ GHWHFWLRQ RI /26 /2) RU /RVV RI 2SWLFDO &DUULHU /23& FRQGLWLRQV (QDEOHV H[WUDFWLRQ RI WKH HQWLUH 6HFWLRQ RYHUKHDG YLD WKH 5HFHLYH 2YHUKHDG $FFHVV 3RUW 52$3 ([WUDFWV - ( ) DQG '' RFWHWV IURP 6HFWLRQ RYHUKHDG DQG VXEVHTXHQWO\ LQVHUWV WKHP LQWR RFWHWV RQ VSHFLDO SXUSRVH RXWSXW SRUWV LQ WKH 52$3 EORFN

621(76'+ 6HFWLRQ3DWK 7UDFH %XIIHUV 667%637% 5HFHLYH )XQFWLRQV &KHFNV UHFHLYHG 6HFWLRQ WUDFH PHVVDJHV IRU SHUVLVWHQF\ DQG LVVXHV D PLVPDWFK DODUP LI UHTXLUHG
Page 10
1.0 Product Description.
G56054-0, Rev 1.0
SONET/SDH 2.5Gbps Transport Terminating Transceiver
VSC9142.
6XSSRUWV WKUHH GLIIHUHQW 6HFWLRQ WUDFH PHVVDJH IRUPDWV WUDQVSRUWHG LQ WKH - RFWHW LQ ERWK WKH WUDQVPLW DQG UHFHLYH GLUHFWLRQV LH VLQJOH RFWHW 621(7 PHVVDJHV RFWHW 6'+ PHVVDJHV RU RFWHW 621(7 &//, PHVVDJHV
621(76'+ /LQH 2YHUKHDG 7HUPLQDWLRQ 5/23 ([WUDFWV DQG ILOWHUV /LQH 5HPRWH 'HIHFW ,QGLFDWLRQ 5',/ DQG /LQH $ODUP ,QGLFDWLRQ 6LJQDO $,6/ DODUPV IURP UHFHLYHG . RFWHWV VXSSRUWV SURJUDPPDEOH ILOWHULQJ FRQVWUDLQWV 'HWHFWV DQG DFFXPXODWHV /LQH %,3 HUURUV IURP UHFHLYHG % RFWHWV VXSSRUWV ERWK LQGLYLGXDO DQG EORFNPRGH DFFXPXODWLRQ 'HWHFWV DQG DFFXPXODWHV /LQH 5HPRWH (UURU ,QGLFDWLRQV 5(,/ IURP UHFHLYHG 0 RFWHWV VXSSRUWV ERWK LQGLYLGXDO DQG EORFNPRGH DFFXPXODWLRQ ([WUDFWV DQG ILOWHUV 6\QFKURQL]DWLRQ 6WDWXV 66 IURP UHFHLYHG 6 RFWHWV VXSSRUWV XQVWDEOHPLVPDWFK DODUPV DQG SURJUDPPDEOH ILOWHULQJ FRQVWUDLQWV ([WUDFWV DQG ILOWHUV .. $XWRPDWLF 3URWHFWLRQ 6ZLWFKLQJ $36 RFWHWV VXSSRUWV XQVWDEOH DODUPV DQG SURJUDPPDEOH ILOWHULQJ FRQVWUDLQWV 2SWLRQDOO\ H[WUDFWV /LQH RYHUKHDG YLD WKH SRUWV LQ WKH 52$3 EORFN ([WUDFWV '' 6 ( DQG .. RFWHWV IURP /LQH RYHUKHDG DQG VXEVHTXHQWO\ LQVHUWV WKHP LQWR RFWHWV RQ WKH VSHFLDO SXUSRVH RXWSXW SRUWV LQ WKH 52$3 EORFN

621(76'+ 2YHUKHDG ([WUDFWLRQ 3RUW 52$3 3URYLGHV WZR LGHQWLFDO LQGHSHQGHQW VSHFLDO SXUSRVH SRUWV WR HQDEOH H[WUDFWLRQ RI VSHFLDO SXUSRVH RFWHWV DQG FHUWDLQ 621(76'+ DODUPV VSHFLILF WR $XWRPDWLF 3URWHFWLRQ 6ZLWFKLQJ $36 IURP WKH WUDQVSRUW RYHUKHDG 2XWSXWV WKH 563)3 IUDPH SXOVH VLJQDO DV ZHOO DV FORFNV DQG FRQWURO VLJQDOV DVVRFLDWHG ZLWK HDFK RXWSXW VWUHDP (QDEOHV DFTXLVLWLRQ RI WKH HQWLUH 6HFWLRQ/LQH WUDQVSRUW RYHUKHDG YLD WKH QLEEOH RXWSXW SRUW 572+>@
621(76'+ 3DWK 2YHUKHDG 7HUPLQDWLRQ 5323
4.0 Electrical & Mechanical Data
Page 11.
G56054, Rev 1.0
STS-48c Physical Layer Packet/ATM Over SONET/SDH Device
VSC9142
([WUDFWV DQG LQWHUSUHWV + + SRLQWHU RFWHWV ZKLFK DUH XVHG WR GHILQH WKH 621(7 63( V\QFKURQRXV SD\ORDG HQYHORSH RU 6'+ 9& YLUWXDO FRQWDLQHU DFFRUGLQJ WR $16, 7 DQG ,787 * UHFRPPHQGDWLRQV 0RQLWRUV + + RFWHWV IRU FRQFDWHQDWLRQ LQGLFDWLRQ &, 3URYLGHV GLDJQRVWLF SRLQWHU IXQFWLRQV 6XSSRUWV 3DWK $ODUP ,QGLFDWLRQ 6LJQDO $,63 DQG /RVV RI 3RLQWHU /233 DODUP GHFODUDWLRQ 'HWHFWV DQG DFFXPXODWHV 3DWK %,3 HUURUV IURP UHFHLYHG % RFWHWV VXSSRUWV ERWK LQGLYLGXDO DQG EORFNPRGH DFFXPXODWLRQ 'HWHFWV DQG DFFXPXODWHV 3DWK 5HPRWH (UURU ,QGLFDWLRQV 5(,3 IURP UHFHLYHG * RFWHWV VXSSRUWV ERWK LQGLYLGXDO DQG EORFNPRGH DFFXPXODWLRQ 8S WR LQGLYLGXDO HUURUV FDQ EH GHWHFWHG SHU VHFRQG 3URJUDPPDEOH GHWHFWLRQ RI 3DWK 5HPRWH 'HIHFW ,QGLFDWLRQV 5',3 IURP UHFHLYHG * RFWHWV 3URJUDPPDEOH GHWHFWLRQ DQG DODUP JHQHUDWLRQ IRU 3DWK 6LJQDO /DEHO IURP UHFHLYHG & RFWHWV

3DFNHW 3URFHVVLQJ DQG 0RQLWRULQJ 533 3URJUDPPDEOH LGHQWLILFDWLRQ RI WKH +'/& )ODJ 6HTXHQFH 3URJUDPPDEOH GHWHFWLRQ DQG GLVFDUG RI LQYDOLG IUDPHV 3URJUDPPDEOH H[SHFWHG &RQWURO (VFDSH DQG 2FWHW 'HVWXIILQJ 0DVN 3URJUDPPDEOH H[SHFWHG $GGUHVV DQG &RQWURO ILHOGV 3URJUDPPDEOH 3URWRFRO ILHOG GHFODUDWLRQ DQG SURFHVVLQJ 'HWHFWV $ERUW 6HTXHQFH LQ LQFRPLQJ +'/& IUDPHV 9HULILHV WKH UHFHLYHG )UDPH &KHFN 6HTXHQFH )&6 ILHOG 7KH )UDPH &KHFN 6HTXHQFH )&6 FDQ EH JHQHUDWHG XVLQJ WZR PHWKRGV 8VLQJ WKH ELW &5&&&,77 JHQHUDWLQJ SRO\QRPLDO [ [ [

Page 12
1.0 Product Description.
G56054-0, Rev 1.0
SONET/SDH 2.5Gbps Transport Terminating Transceiver
VSC9142.
8VLQJ WKH ELW &5& JHQHUDWLQJ SRO\QRPLDO [[ [ [ [ [ [ [ [ [ [ [ [ [

'HVFUDPEOHV UHFHLYHG GDWD XVLQJ VHOIV\QFKURQL]LQJ VFUDPEOHU 666 SRO\QRPLDO [ IXOO DQGRU SDUWLDO GHVFUDPEOLQJ FDQ EH LQGHSHQGHQWO\ HQDEOHG RU GLVDEOHG 3URJUDPPDEOH ORQJ DQG VKRUWSDFNHW FKHFNLQJ 3URJUDPPDEOH VXSSRUW IRU 6HOI 'HVFULELQJ 3DGGLQJ 2SWLRQDO VWRUDJH RI 333 3URWRFRO ILHOG LQ 5[ ),)2

ZRUG 5[ ),)2 DFFRPPRGDWHV XS WR 333 3URWRFRO,QIRUPDWLRQ ILHOG RFWHWV 7ZR GLIIHUHQW SURJUDPPDEOH GHILQLWLRQV IRU UHFHLYHG HUURUHG +'/& IUDPHV 3URJUDPPDEOH SDFNHW GLVFDUG DQG HUURU PDUNLQJ ILOWHU ELW SHUIRUPDQFH PRQLWRULQJ FRXQWHUV WR REVHUYH $ERUWHG +'/& IUDPHV UHFHLYHG )&6 HUURUHG +'/& IUDPHV UHFHLYHG (PSW\ +'/& IUDPHV UHFHLYHG 5HFHLYHG +'/& IUDPHV ZLWK $GGUHVV&RQWUROFRPSUHVVLRQ IRXQG /RQJ RU VKRUW SDFNHWV UHFHLYHG ,QYDOLG IUDPHV UHFHLYHG 2FWHWV UHFHLYHG EHIRUH RU DIWHU RFWHW GHVWXIILQJ )UDPHV UHFHLYHG H[FOXGLQJ LQYDOLG IUDPHV 3DFNHWV GLVFDUGHG E\ ODEHO ILOWHULQJ (UURUPDUNHG SDFNHWV IURP ODEHO ILOWHULQJ 3DFNHWV VWRUHG LQ WKH 5[ ),)2 (UURUPDUNHG SDFNHWV VWRUHG LQ WKH 5[ ),)2 3DFNHW RFWHWV VWRUHG LQ WKH 5[ ),)2 333 SDGGLQJ RFWHWV UHFHLYHG 63( 7UDQVSDUHQW 0RGH SDVVHV WKH 621(7 676F 63( RU 6'+ 670 $8F SD\ORDG GLUHFWO\ WR WKH 5[ ),)2 ZLWKRXW SURFHVVLQJ
$70 &HOO 'HPDSSLQJ 5$&3
4.0 Electrical & Mechanical Data
Page 13.
G56054, Rev 1.0
STS-48c Physical Layer Packet/ATM Over SONET/SDH Device
VSC9142
&HOO 'HOLQHDWLRQ LV FRPSOHWHG XVLQJ D VKRUWHQHG F\FOLF FRGH ZLWK WKH JHQHUDWLQJ SRO\QRPLDO [ [ [ 7KH FRVHW SRO\QRPLDO [ [ [ EH DGGHG WR WKH FDOFXODWHG +(& FKHFN ELWV EHIRUH FRPSDULVRQ
AFDQ
6XSSRUWV VLQJOHELW KHDGHU HUURU FRUUHFWLRQ DV ZHOO DV SURJUDPPDEOH FHOO GURSSLQJ GXULQJ VLQJOH RU PXOWLSOH HUURU GHWHFWLRQ 2SWLRQDO GHVFUDPEOLQJ RI WKH RFWHW LQIRUPDWLRQ ILHOG XVLQJ WKH VHOIV\QFKURQL]LQJ GHVFUDPEOHU SRO\QRPLDO [

&HOO ILOWHULQJ YLD SURJUDPPDEOH *)& 37, RU &/3 ILHOGV 'HWHFWLRQ DQG PRQLWRULQJ RI FRUUHFWDEOH DQG XQFRUUHFWDEOH +(& HUURUV DV ZHOO DV WKH QXPEHU RI FHOOV ZULWWHQ WR WKH 5[ ),)2 5[ ),)2 DFFRPPRGDWHV XS WR HLJKW $70 FHOOV
8723,$/HYHO 3263+< &HOO3DFNHW 5HFHLYH ,QWHUIDFH 3,)8,) 6WDQGDUGVFRPSOLDQW 326 SDFNHW RYHU 621(76'+ LQWHUIDFH 3URJUDPPDEOH SDULW\ ELW HYHQ RU RGG ,QWHUIDFH VXSSRUWV ERWK ZRUG DQG FHOOSDFNHWOHYHO WUDQVIHU PRGHV 6LQJOH 3+< 8723,$ OLNH LQWHUIDFH IRU $70 DSSOLFDWLRQV 5[ ),)2 UHVHW RU IOXVK YLD WKH &38 LQWHUIDFH
1.2.3
Microprocessor Interface (CPU)
5HDGZULWH VXSSRUW IRU DOO FRQILJXUDWLRQ ELWV DQG DFFHVV UHJDUGOHVV RI GHYLFH FORFN VRXUFH VWDWXV H[FHSW UHVHW VWDWH &RQILJXUDWLRQ ELWV LQFOXGH VHOHFWLRQ ELWV LQWHUUXSW PDVNLQJ ELWV DQG SURJUDPPDEOH FRXQWHUFRQWURO YDOXHV 3URYLGHV HLJKW SURJUDPPDEOH *HQHUDO 3XUSRVH ,QSXW2XWSXW *3,2 SRUWV IRU PRQLWRULQJ DQG FRQWUROOLQJ H[WHUQDO VLJQDOV $OO *3,2V VXSSRUW ELVWDEOH LQWHUUXSWV ZKHQ FRQILJXUHG DV LQSXW SRUWV
Page 14
1.0 Product Description.
G56054-0, Rev 1.0
SONET/SDH 2.5Gbps Transport Terminating Transceiver
VSC9142.
&ORFN DFWLYLW\ PRQLWRUV DUH DYDLODEOH RQ DOO LQSXW FORFNV
1.2.4
JTAG Test Access Port (JTAG TAP)
7KH -7$* WHVW DFFHVV SRUW 7$3 HQDEOHV H[WHUQDO ERXQGDU\ VFDQ WR EH SHUIRUPHG LQ FRPSOLDQFH ZLWK WKH ,((( 6WDQGDUG 7HVW 3RUW DQG %RXQGDU\ 6FDQ $UFKLWHFWXUH 6WDQGDUG
1.2.5
Bit Error Rate Monitor (BERM)
%LW HUURU UDWH PRQLWRULQJ EDVHG RQ /LQH %,3 % RFWHW HUURU FRGHV PHDVXUHPHQW SUHFLVLRQ GRZQ WR
)RXU LQGHSHQGHQW %(5 PRQLWRUV ZLWK LQGLYLGXDO SURJUDPPDEOH DFFXPXODWLRQ SHULRGV VDWXUDWLRQ WKUHVKROGV LH PD[LPXP QXPEHU RI HUURUV WKDW FDQ EH DFFXPXODWHG SHU IUDPH DQG DODUP WKUHVKROGV %(5 6LJQDO 'HJUDGH %(56' DODUP LV SURYLGHG IRU %(5 PRQLWRUV DQG %(5 6LJQDO )DLO %(56) DODUP LV SURYLGHG IRU %(5 PRQLWRUV DQG

1.3 Applications
7KH 96& IDFLOLWDWHV WKH GHYHORSPHQW RI KLJKO\LQWHJUDWHG VLQJOHERDUG 676670 ZLWK FRQFDWHQDWHG SD\ORDG WR SDFNHW$70 LQWHUIDFH OLQH FDUGV ,Q WKH 326 SDFNHW RYHU 621(7 PRGH WKH GHYLFH FDQ EH XVHG WR LQWHUFRQQHFW ,3333+'/& HTXLSPHQW WR SXEOLF RU SULYDWH 621(76'+ QHWZRUNV 6LPLODUO\ LQ WKH $70 RYHU 621(7 $70 PRGH WKLV GHYLFH FDQ EH XVHG WR LQWHUFRQQHFW $70 VZLWFKHV 7KH 96& LV DQ LGHDO SODWIRUP IRU GHYHORSLQJ KLJKO\LQWHJUDWHG VZLWFKHV URXWHUV KXEV :$1 HTXLSPHQW DQG WHVW V\VWHPV
1.3.1
Typical System Utilization
6LQFH WKH 96& FRQWDLQV DOO QHFHVVDU\ SK\VLFDO LQWHUIDFH EORFNV WKH GHYLFH FDQ PDWH GLUHFWO\ WR WKH 2SWLFDO WUDQVFHLYHU )LJXUH VKRZV D WRSOHYHO YLHZ RI D W\SLFDO $70 RU SDFNHW RYHU 621(7 DSSOLFDWLRQ IRU WKH 96&
4.0 Electrical & Mechanical Data
Page 15.
G56054, Rev 1.0
STS-48c Physical Layer Packet/ATM Over SONET/SDH Device
VSC9142
Fibre Optic Tx Fibre Optic XCVR Fibre Optic Rx
Clock (Optional) Data
CMU Crystal
ATM/Packet Layer VSC9142 2.5 Gb/s POS/ATM UNI
CRU Crystal
Data
CPU I/F
Figure1.2. Typical ATM- or packet-to-SONET Interface Application
1.3.2
Loopback Configurations
6\VWHP GHYHORSPHQW DQG WHVW DUH VLPSOLILHG YLD ILYH LQWHUQDO ORRSEDFN PRGHV 7KHVH LQFOXGH HTXLSPHQW IDFLOLW\ VHFWLRQ OLQH DQG SDFNHW8723,$ ORRSV VHH )LJXUH 7KH 96&*V IDFLOLW\ ORRSEDFN PRGH HQDEOHV WKH GHYLFH WR EH XVHG IRU UHJHQHUDWLRQ DSSOLFDWLRQV ,Q WKLV FDSDFLW\ FRQQHFWLRQV WR WKH GHYLFH*V GURS VLGH DUH QRW UHTXLUHG ,Q HTXLSPHQW DQG GURS ORRS PRGHV H[WHUQDO FORFN VRXUFHV DUH PX[HG LQWHUQDOO\ )DFLOLW\ /RRSEDFN FRQQHFWV WKH 3+< EORFN UHFHLYH LQSXW SRVW GHPXOWLSOH[LQJ EDFN WR WKH 3+< WUDQVPLW RXWSXW 7KH UHFHLYH DQG WUDQVPLW FRUH FORFNV PXVW EH IUHTXHQF\ ORFNHG YLD ORRSWLPLQJ RU UHJLVWHU FRQILJXUDWLRQ (TXLSPHQW /RRSEDFN FRQQHFWV WKH GDWD SDWK RXWSXW IURP WKH 7623 EORFN WUDQVPLW GLUHFWLRQ EDFN WR WKH LQSXW RI WKH 5623 EORFN UHFHLYH GLUHFWLRQ 7KH UHFHLYH FRUH FORFN PXVW EH VHW HTXDO WR WKH WUDQVPLW FRUH FORFN YLD ORRSWLPLQJ RU UHJLVWHU FRQILJXUDWLRQ /LNHZLVH 5)&/. DQG 7)&/. DUH UHTXLUHG WR EH IUHTXHQF\ ORFNHG 6HFWLRQ /RRSEDFN FRQQHFWV WKH GDWD SDWK RXWSXW IURP WKH 5623 EORFN WR WKH LQSXW RI WKH 7623 EORFN 7KH UHFHLYH DQG WUDQVPLW FRUH FORFNV PXVW EH IUHTXHQF\ ORFNHG /LQH /RRSEDFN FRQQHFWV WKH GDWD SDWK RXWSXW IURP WKH 5/23 EORFN WR WKH LQSXW RI WKH 7/23 EORFN 7KH UHFHLYH DQG WUDQVPLW FRUH FORFNV PXVW EH IUHTXHQF\ ORFNHG 3DFNHW&HOO /RRSEDFN FRQQHFWV WKH RXWSXW IURP WKH 7[ ),)2 LQ WKH 7337$3& EORFN WR WKH LQSXW RI WKH 5[ ),)2 LQ WKH 5335$3& EORFN 7KH UHFHLYH DQG WUDQVPLW FRUH FORFNV DUH UHTXLUHG WR EH IUHTXHQF\ ORFNHG

Page 16
1.0 Product Description.
G56054-0, Rev 1.0
SONET/SDH 2.5Gbps Transport Terminating Transceiver
VSC9142.
TOAP
JTAG TAP
PHY TSOP TLOP TPOP TPP/TACP
PIF/UIF
Equipment Loopback
Facility Loopback
Section Loopback
Line Loopback
SSTB
SPTB
RSOP
RLOP
RPOP RPP/RACP
ROAP
Packet/Cell Loopback
BERM CPU
Figure1.3. VSC9142 Internal Loopback Paths
4.0 Electrical & Mechanical Data
Page 17.
G56054, Rev 1.0
STS-48c Physical Layer Packet/ATM Over SONET/SDH Device
VSC9142
1.4 Pin Definitions
)LJXUH LGHQWLILHV WKH H[WHUQDO EDOO SDGV LQ WKH SLQ %*$ SDFNDJH 7DEOH SURYLGHV D GHWDLOHG IXQFWLRQDO GHVFULSWLRQ RI DOO KDUGZDUH VLJQDO SLQV LQ WKH GHYLFH
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD
A1 BALL PAD CORNER
BOTTOM VIEW
DIE SIDE
Figure1.4. VSC9142 320 BGA Ball Pad Identification
Page 18
1.0 Product Description.
G56054-0, Rev 1.0
SONET/SDH 2.5Gbps Transport Terminating Transceiver
VSC9142. Table1.1. Hardware Signal Definitions (1 of 12)
Pin Label
RLINSERRLINSER+ RLIN4[0]RLIN4[0]+ RLIN4[1]RLIN4[1]+ RLIN4[2]RLIN4[2]+ RLIN4[3]RLIN4[3]+ RLPRTY4RLPRTY4+
Pad
F24 G24 D22 E21 E22 D23 F21 F22 E23 F23 C22 C23
I/O
I I
Type
PECL LVDS
Signal Name
Serial Line Receive Data Parallel Line Receive Data Serial line data input.
Description
This is the parallel line-side receive data bus for the incoming STS-48c/STM-16 AU-4-16c data stream. RLIN4[3] is the most significant and first bit arriving bit on the serial data stream. RLIN4[3..0] is sampled on the rising edge of RLCLK4+. RLIN4[3..0]+ are the true signal values.
I
LVDS
Parallel Line Receive Parity
RLCLK4RLCLK4+
D24 C24
I
LVDS
Parallel Line Receive Clock
RLINSERMID
H23
I
N/A
Serial Line Receive Data Center Tap
CRUREFCLKCRUREFCLK+ CRUREFDET CRULOCKDET
J21 J22 AD15 AC15
I O O
PECL TTL TTL
CRU Reference Clock CRU Reference Clock Detect CRU Lock Detect
CRUREFSEL1 CRUREFSEL0
AB15 AA15
I
TTL
CRU Reference Clock Select
CRURECCLKCRURECCLK+ CRUFILTERCRUFILTER+
K24 J24 L23 K22
O
PECL
CRU Recovered Clock CRU Loop Filter
I
N/A
CRUREFOUTSEL
AD16
I
TTL
CRURECCLK Output Selector
This is a programmable (even/odd) parity bit for parallel line receive data RLIN4[3..0]. RLPRTY4 is sampled on the rising edge of RLCLK4+. RLPRTY4+ is the true signal value. This is the reference clock input for the parallel line-receive data carried in RLIN4[3..0]+/-. The nominal frequency is 622.08 MHz for STS-48c/STM-16 AU-4-16c operation. RLCLK4+ is the true signal value. RLINSER+/- has a 100 ohms on-chip resistor termination which has a center tap between the two 50 ohm resistors. The center tap can be used to bias the centerpoint for single ended applications or decoupled to GND for differential applications. This input is the reference clock used within phase locked loop in the clock recovery unit. This output indicates the presense of clock transistions on CRUREFCLK+/-. The signal is active high. This output indicatest the lock status of the PLL within the CRU with respect to CRUREFCLK+/-. The signal is active high. These inputs select which frequency is to be expected on CRUREFCLK+/-. The binary combination of the two pins are described below (CRUREFSEL0 noted first). 00 78 MHz 01 155 MHz 10 311 MHz This reference clock output is derived from the 2.5 Gb/s reference clock divided down according to CRUREFSEL[1..0]. These inputs are brought off-chip to connect to a capacitor which completes the CRU loop filter. CRUFILTER+ should be connected to one side of a 0.1uF capacitor while CRUFILTER- should be connected to the other side of the capacitor. This input selects the clock to be output on pins CRURECCLK+/-. A high level selects a looped version of the reference clock, while a low level selects the divided version of the recovered clock.
4.0 Electrical & Mechanical Data
Physical Interface (PHY) Signals
Page 19.
G56054, Rev 1.0
STS-48c Physical Layer Packet/ATM Over SONET/SDH Device
VSC9142
Table 1.1
Hardware Signal Definitions (2 of 12)
Pad
N24 M24 R24 P24 V23 V22 V24 W23 Y22 W21 AA24 AA23 U23 U22
Pin Label
TLOUTSERTLOUTSER+ TLCLKSERTLCLKSER+ TLOUT4[0]TLOUT4[0]+ TLOUT4[1]TLOUT4[1]+ TLOUT4[2]TLOUT4[2]+ TLOUT4[3]TLOUT4[3]+ TLPRTY4TLPRTY4+
I/O
O O O
Type
PECL PECL LVDS
Signal Name
Serial Line Transmit Data Serial Line Transmit Clock Parallel Line Transmit Data Serial line data output. Serial line clock output
Description
This is the parallel line-side transmit data bus for the outgoing STS-48c/STM-16 AU-4-16c data stream. TLOUT4[3] is the most significant and first transmitted bit in the serial data stream. TLOUT4[3..0] is latched out the rising edge of TLCLK4+, but is centered about TLCLK4O-. TLOUT[3..0]+ are the true signal values.
Physical Interface (PHY) Signals (cont.)
O
LVDS
Parallel Line Transmit Parity
TLCLK4TLCLK4+
T24 U24
I
LVDS
Parallel Line Transmit Clock
TLCLK4OTLCLK4O+
Y24 W24
O
LVDS
Parallel Line Transmit Clock Out CMU Reference Clock CMU Reference Clock Detect CMU Lock Detect
CMUREFCLKCMUREFCLK+ CMUREFDET CMULOCKDET
N23 M23 AC17 AC16
I O O
PECL TTL TTL
CMUREFSEL1 CMUREFSEL0
AB16 AA16
I
TTL
CMU Reference Clock Select
CMUFILTERCMUFILTER+
L22 L21
I
N/A
CMU Loop Filter
This is a programmable (even/odd) parity bit for parallel line transmit data TLOUT4[3..0]. TLPRTY4 is latched out on the rising edge of TLCLK4+, but is centered about TLCLK4O-. TLPRTY4+ is the true signal value. This is the reference clock input for the parallel line-transmit data carried in TLOUT4[3..0]+/-. The nominal frequency is 622.08 MHz for STS-48c/STM-16 AU-4-16c operation. TLCLK4+ is the true signal value. This output is the looped version of the reference clock input TLCLK4+/-. The nominal frequency is 622.08 MHz for STS48c/STM-16 AU-4-16c operation. TLCLK4O+ is the true signal value. This input is the reference clock used for the clock multiplier unit. This output indicates the presense of clock transistions on CMUREFCLK+/-. The signal is active high. This output indicatest the lock status of the PLL within the CMU with respect to CMUREFCLK+/-. The signal is active high. These inputs select which frequency is to be expected on CMUREFCLK+/-. The binary combination of the two pins are described below (CMUREFSEL0 noted first). 00 78 MHz 01 155 MHz 10 311 MHz These inputs are brought off-chip to connect to a capacitor which completes the CMU loop filter. CMUFILTER+ should be connected to one side of a 0.1uF capacitor while CMUFILTERshould be connected to the other side of the capacitor.
Page 20
1.0 Product Description.
G56054-0, Rev 1.0
SONET/SDH 2.5Gbps Transport Terminating Transceiver
VSC9142.
Table 1.1
Hardware Signal Definitions (3 of 12)
Pad
AC12
Pin Label
CLKRSTEN
I/O
I
Type
TTL
Signal Name
Clock Reset Enable
Description
Asserting CLKRSTEN halts all primary clock outputs (TXRCLK, RXRCLK, RSPCLK1, RSPCLK2, RTOHCLK, TSPCLK1, TSPCLK2, and TTOHCLK) during master reset. If deasserted, all primary clock outputs run normally during master reset. This input enables looptiming which forces the CMU and subsequent Tx clocks to be referenced to the recovered line clock. This signal is active high although the associated register can override the pin. This input is used to monitor the optical carrier signal status, and detected changes which can be used to generate interrupts. This enables the optical signal to be monitored via the device CPU interface. When LOPC is asserted, the receive processor is optionally clocked by the transmit clock (derived from TLCLK4+/- or the CMU clock). This input selects the 4 bit interface and disables the CRU and CMU. This input is active high.
LOOPTIMING
AD18
I
TTL
Looptime Enable
Physical Interface (PHY) Signals (cont.)
LOPC
AC13
I
TTL
Loss of Optical Carrier
PHY4BITSEL
AB14
I
TTL
4-Bit Physical Interface Select
TLSYNCLVDSTLSYNCLVDS+
T22 T21
I
LVDS
Transmit Synchronization
TLSYNCTTL
AB23
I
TTL
Transmit Synchronization
RXRCLK
AD12
O
TTL
Receive Reference Clock
This is the LVDS input for the synchronous reset signal for the line-side transmit processor. (NOTE: TLSYNCLVDS/ TLSYNCTTL is intended for use in STS-192/STM-64 applications only.) This is the TTL input for the synchronous reset signal for the line-side transmit processor. (NOTE: TLSYNCLVDS/ TLSYNCTTL is intended for use in STS-192/STM-64 applications only.) This reference clock output is derived from the serial or parallel receive line clock and can be programmed to operate at 78MHz, 38MHz, 19MHz, or 8kHz frequencies. This reference clock output is derived from the serial or parallel transmit line clock and can be programmed to operate at 78MHz, 38MHz, 19MHz, or 8kHz frequencies.
TXRCLK
B21
O
TTL
Line Transmit Reference Clock
4.0 Electrical & Mechanical Data
Page 21.
G56054, Rev 1.0
STS-48c Physical Layer Packet/ATM Over SONET/SDH Device
VSC9142
Table 1.1
Hardware Signal Definitions (4 of 12)
Pad
J3 J4 H3 G1 G2 G3 F1 F2 F3 E2 E3 F4 D1 D2 D3 E4 C1 C2 D5 B3 A3 C4 B4 D6 C5 A4 C6 B5 B6 C7 A6 D9
Pin Label
TDAT/TUDATA[0] TDAT/TUDATA[1] TDAT/TUDATA[2] TDAT/TUDATA[3] TDAT/TUDATA[4] TDAT/TUDATA[5] TDAT/TUDATA[6] TDAT/TUDATA[7] TDAT/TUDATA[8] TDAT/TUDATA[9] TDAT/TUDATA[10] TDAT/TUDATA[11] TDAT/TUDATA[12] TDAT/TUDATA[13] TDAT/TUDATA[14] TDAT/TUDATA[15] TDAT/TUDATA[16] TDAT/TUDATA[17] TDAT/TUDATA[18] TDAT/TUDATA[19] TDAT/TUDATA[20] TDAT/TUDATA[21] TDAT/TUDATA[22] TDAT/TUDATA[23] TDAT/TUDATA[24] TDAT/TUDATA[25] TDAT/TUDATA[26] TDAT/TUDATA[27] TDAT/TUDATA[28] TDAT/TUDATA[29] TDAT/TUDATA[30] TDAT/TUDATA[31]
I/O
I
Type
TTL
Signal Name
Transmit Packet Data Bus (TDATx) or UTOPIA Transmit Cell Data Bus (TUDATAx)
Description
POS Mode: This 32-bit data bus is used to drive four-octet true data from the Packet to PHY layer. TDAT[31] is the MSB. Packets are aligned to the 32-bit TDATx boundary. ATM Mode: This 32-bit data bus is used to drive four-octet true data from the ATM to PHY layer. TUDATA[31] is the MSB.
Page 22
Drop Side (PIF/UIF) Transmit Signals
1.0 Product Description.
G56054-0, Rev 1.0
SONET/SDH 2.5Gbps Transport Terminating Transceiver
VSC9142.
Table 1.1
Hardware Signal Definitions (5 of 12)
Pad
C8
Pin Label
POS Mode: TPRTY ATM Mode: TUPRTY
I/O
I
Type
TTL
Signal Name
Transmit Bus Parity
Description
POS Mode: TRPRTY is the odd/even (programmable, default odd) parity bit over TDAT[31..0]. The signal is only valid when asserted simultaneously with TENB. ATM Mode: TUPRTY is the odd/even (programmable, default odd) parity bit over TUDATA[31..0], driven by the ATM layer. The signal is valid when asserted simultaneously with TUENB*.
POS Mode: TMOD[1] TMOD[0]
I A7 B7
TTL
Transmit Word Modulo
POS Mode only: These inputs are used to qualify TDATx data octets. The state of TMOD[1,0] defines which of the four TDAT octets contain valid data when both TEOP and TENB are asserted. Non-EOP words always contain four valid TDAT octets. POS Mode: TSOP is asserted (active high) by the Packet layer to indicate that TDATx contains the first valid octet of a new packet. The signal is valid when asserted simultaneously with TENB. The packet interface can be operated without using this signal. ATM Mode: TUSOC is asserted (active high) by the ATM layer to indicate that TUDATAx contains the first valid octet of the cell. The signal is only valid when asserted simultaneously with TUENB*. POS Mode only: TEOP is asserted (active high) by the Packet layer to indicate that TDATx contains the last valid octet of the packet. Only valid when asserted simultaneously with TENB. POS Mode: DTPA transitions high when a programmable minimum number of octets are available in the Tx FIFO. Once high, the DTPA indicates that the Tx FIFO is not full. When DTPA transitions low, it optionally indicates that the Tx FIFO is full or near full. ATM Mode: TUFULL*/TUCLAV is indicates "Full" or "Cell Available" status of UTOPIA transmit interface for flow control. TUFULL* is for word-level flow control; TUCLAV is for cell-level flow control. Polarity is selectable via an internal register bit (i.e., TUFULL* active low/TUCLAV active high, or vice versa). POS Mode only: An active TERR flag can be used to force HDLC frame abortion, or insertion of FCS error in the transmitted HDLC/PPP frames. The TERR value is only valid for TEOP-marked words, and is ignored for all other word writes. POS Mode: TENB is used by the Packet layer to indicate cycles when TDATx contains valid packet data (active low). ATM Mode: TUENB* is used by the ATM layer to indicate cycles when TUDATAx contains valid cell data (active low).
POS Mode: TSOP ATM Mode: TUSOC
C9
I
TTL
Drop Side (PIF/UIF) Transmit Signals (cont.)
Transmit Start of Packet or UTOPIA Transmit Start of Cell
POS Mode: TEOP POS Mode: DTPA ATM Mode: TUFULL*/ TUCLAV
D10
I
TTL
Transmit End of Packet Transmit PolledPHY Packet Available or Transmit Full/Cell Available
A9
O
TTL
POS Mode: TERR
B9
I
TTL
Transmit Error Indicator
POS Mode: TENB ATM Mode: TUENB* POS Mode: TFCLK ATM Mode: TUCLK POS Mode: TFCLKO ATM Mode: TUCLKO
C10
I
TTL
Transmit Write Enable
A10
I
TTL
Transmit Write Clock
POS Mode: TFCLK is a reference clock provided by the Packet layer to the PHY layer to synchronize transfers on TDATx. ATM Mode: TUCLK is a reference clock provided by the ATM layer to the PHY layer to synchronize transfers on TUDATAx.
B10
O
TTL
Transmit Write Clock Looped
POS Mode: TFCLKO is the TFCLK transfer synchronization reference clock from the Packet layer looped out. ATM Mode: TUCLKO is the TUCLK transfer synchronization reference clock from the ATM layer looped out.
4.0 Electrical & Mechanical Data
Page 23.
G56054, Rev 1.0
STS-48c Physical Layer Packet/ATM Over SONET/SDH Device
VSC9142
Table 1.1
Hardware Signal Definitions (6 of 12)
Pad
W1 V3 V2 V1 U3 U2 T4 T3 T2 T1 R4 R3 R2 R1 P3 P2 N1 N4 N3 N2 M3 M4 M2 M1 L2 L3 K1 K2 K3 K4 J1 J2 Y3
Pin Label
RDAT/RUDATA[0] RDAT/RUDATA[1] RDAT/RUDATA[2] RDAT/RUDATA[3] RDAT/RUDATA[4] RDAT/RUDATA[5] RDAT/RUDATA[6] RDAT/RUDATA[7] RDAT/RUDATA[8] RDAT/RUDATA[9] RDAT/RUDATA[10] RDAT/RUDATA[11] RDAT/RUDATA[12] RDAT/RUDATA[13] RDAT/RUDATA[14] RDAT/RUDATA[15] RDAT/RUDATA[16] RDAT/RUDATA[17] RDAT/RUDATA[18] RDAT/RUDATA[19] RDAT/RUDATA[20] RDAT/RUDATA[21] RDAT/RUDATA[22] RDAT/RUDATA[23] RDAT/RUDATA[24] RDAT/RUDATA[25] RDAT/RUDATA[26] RDAT/RUDATA[27] RDAT/RUDATA[28] RDAT/RUDATA[29] RDAT/RUDATA[30] RDAT/RUDATA[31] POS Mode: RPRTY ATM Mode: RUPRTY POS Mode: RMOD[1] RMOD[0] POS Mode: RSOP ATM Mode: RUSOC
I/O
O
Type
TTL
Signal Name
Recevie Packet Data Bus (RDATx) or Receive Cell Data Bus (RUDATAx)
Description
POS Mode: This 32-bit data bus is used to drive four-octet true data from the PHY to Packet layer. RDAT[31] is the MSB. Packets are aligned to the 32-bit RDATx boundary. ATM Mode: This 32-bit data bus is used to drive four-octet true data from the PHY to ATM layer. RUDATA[31] is the MSB.
Drop Side (PIF/UIF) Receive Signals
O
TTL
Receive Bus Parity
POS Mode: RPRTY is the odd/even (programmable, default odd) parity bit over RDAT[31..0]. ATM Mode: RUPRTY is the odd/even (programmable, default odd) parity bit over RUDATA[31..0]. POS Mode only: These outputs are used to qualify RDATx data octets. The state of RMOD[1,0] defines which of the four RDAT octets contain valid data when REOP is asserted. NonEOP words always contain four valid RDAT octets. POS Mode: RSOP is asserted (active high) by the Packet layer to indicate that RDATx contains the first valid octet of a new packet. The packet interface can be operated without using this signal. ATM Mode: RUSOC is asserted (active high) by the ATM layer to indicate that RUDATAx contains the first valid octet of a cell. This signal is used to support multiple PHY configurations.
O W2 W3 AA1 O
TTL
Receive Word Modulo
TTL
Receive Start of Packet or UTOPIA Receive Start of Cell
Page 24
1.0 Product Description.
G56054-0, Rev 1.0
SONET/SDH 2.5Gbps Transport Terminating Transceiver
VSC9142.
Table 1.1
Hardware Signal Definitions (7 of 12)
Pad
AB2 AA2
Pin Label
POS Mode: REOP POS Mode: RVAL ATM Mode: RUEMPTY*/ RUCLAV
I/O
O O
Type
TTL TTL
Signal Name
Receive End of Packet Receive Data Valid or Receive Empty/Cell Available
Description
POS Mode only: REOP is asserted (active high) to indicate that RDATx contains the last valid octet of the packet. POS Mode: RVAL asserted (active high) indicates that the recevie data signals (RDATx, RSOP, REOP, RMOD, RPRTY, and RERR) are valid. When RAL is low, all receive signals are invalid and must be disregarded. RVAL transitions low when the Rx FIFO is empty or the end of a packet is reached, and data will not be removed from the Rx FIFO while RVAL is low. Once deasserted, RVAL remains so until the current PHY has been deselected. ATM Mode: RUEMPTY*/RUCLAV indicates "Empty" or "Cell Available" status of the UTOPIA receive interface for flow control. RUEMPTY* is for word-level flow control; RUCLAV is for celllevel flow control. Polarity is selectable via an internal register bit (i.e., RUCLAV active high/RUEMPTY* active low, or vice versa).
Drop Side (PIF/UIF) Receive Signals (cont.)
POS Mode: RERR POS Mode: RENB ATM Mode: RUENB*
W4
O
TTL
Receive Error Indicator Receive Read Enable
POS Mode only: An asserted RERR flag (active high) indicates that the packet contained an error (i.e., abort/FCS error). The RERR flag is only asserted during EOP-marked words. POS Mode: RENB is used by the Packet layer to indicate that the RVAL, RSOP, RPRTY, RDATx, RMODx, REOP, and RERR signals will be sampled at the end of the nest cycle (active low). ATM Mode: RUENB* is used by the ATM layer to indicate that RUDATA, RUSOC, and RPRTY will be sampled at the end of the nest cycle (active low).
AA3
I
TTL
POS Mode: RFCLK ATM Mode: RUCLK POS Mode: RFCLKO ATM Mode: RUCLKO
Y4
I
TTL
AA4
O
TTL
Time Stamp Signals
TXTS
AA6
O
TTL
Receive FIFO Write Clock or Receive Write Clock Receive FIFO Write Clock Looped or Receive Write Clock Looped Transmit Time Stamp
POS Mode: RFCLK is a reference clock provided by the Packet layer to the PHY layer to synchronize transfers on RDATx. ATM Mode: RUCLK is a reference clock provided by the ATM layer to the PHY layer to synchronize transfers on RUDATAx. POS Mode: RFCLKO is the RFCLK transfer synchronization reference clock looped out. ATM Mode: RUCLKO is the RUCLK transfer synchronization reference clock looped out. TXTS is an active high pulse generated when a cell/packet exits the TPP block. The difference in time between a TXTS pulse and a TSOP/TUSOC pulse can be used to determine transmit FIFO latency. RXTS is an active high pulse generated when a new cell/packet arrives in the RPP block. The difference in time between an RXTS pulse and an RSOP/RUSOC pulse is used to determine receive FIFO latency. This is a status signal for loss of signal (LOS) detection (active high). LOS status is also indicated by an internal register bit. This is a status signal for loss of frame (LOF) detection (active high). LOF status is also indicated by an internal register bit. This signal is asserted when the cell delineation state machine is not in SYNC state. This alarm indication is also available via internal register access.
RXTS
AC3
O
TTL
Receive Time Stamp
Rx Alarm Signals
LOS LOF LCD-P
AB5 AA13 AB4
O O O
TTL TTL TTL
Loss of Signal Loss of Frame Loss of Cell Delineation
4.0 Electrical & Mechanical Data
Page 25.
G56054, Rev 1.0
STS-48c Physical Layer Packet/ATM Over SONET/SDH Device
VSC9142
Table 1.1
RSPFP
Hardware Signal Definitions (8 of 12)
Pad
C18
Pin Label
I/O
O
Type
TTL
Signal Name
Receive Special Purpose Frame Pulse Receive Special Purpose Clock 1 Receive Special Purpose Data 1 Receive Special Purpose Valid 1
Description
This is a frame reference for special purpose serial output ports RSPDATx. RSPFP outputs a single clock-cycle-wide pulse coincident with the first bit on the serial data streams. Active high, RSPFP transitions occur on falling edges of RSPCLKx. x =[1,2] This is a clock reference for RSPDAT1 on special purpose serial output port 1. The frequency is 2.16MHz with a 50% duty cycle (optionally gapped to match the bandwidth of RSPDAT1). This is the data output for receive special purpose serial port 1. RSPDAT1 transitions occur on the falling edge of RSPCLK1. This is a status signal for receive transport overhead port 1. RSPVALID1 is asserted when valid data is present on RSPDAT1 (programmable active state). Transitions occur on RSPCLK1 falling edges. This is a clock reference for RSPDAT2 on special purpose serial output port 2. The frequency is 2.16MHz with a 50% duty cycle (optionally gapped to match the bandwidth of RSPDAT2). This is the data output for receive special purpose serial port 2. RSPDAT2 transitions occur on the falling edge of RSPCLK2. This is a status signal for receive transport overhead port 2. RSPVALID2 is asserted when valid data is present on RSPDAT2 (programmable active state). Transitions occur on RSPCLK2 falling edges. This is a clock reference for RTOH[3..0] on the receive transport overhead port. The frequency is 38.88MHz (50% duty cycle). This is the valid status signal for the receive transport overhead port. RTOHVALID is asserted when valid data is present on RTOH[3..0] (programmable active state). RTOHVALID changes on the falling edge of RTOHCLK. This is a frame reference for the receive transport overhead port. RTOHFP outputs a single-cycle-wide pulse coincident with the first bit(s) of the first A1 octet output on RTOH[3..0]. RTOHFP transitions occur on the falling edge of RTOHCLK. These are the data outputs for the receive transport overhead (Section and Line) octets extracted from the incoming STS-48 data stream. RTOH[3..0] carries the entire transport ovehead in the order the octets are received. The most significant nibble (first received) is output first. RTOH[3] is the most significant bit. RTOH[3..0] transitions occur on the falling edge of RTOHCLK.
RSPCLK1
A19
O
TTL
Rx Overhead Transport Access Processor (ROAP) Signals
RSPDAT1
D20
O
TTL
RSPVALID1
C20
O
TTL
RSPCLK2
B18
O
TTL
Receive Special Purpose Clock 2 Receive Special Purpose Data 2 Receive Special Purpose Valid 2
RSPDAT2 RSPVALID2
C17 B17
O O
TTL TTL
RTOHCLK RTOHVALID
B16 B19
O O
TTL TTL
Receive Transport Overhead Clock Receive Transport Overhead Valid
RTOHFP
A18
O
TTL
Receive Transport Overhead Frame Pulse Receive Transport Overhead Data
RTOH[0] RTOH[1] RTOH[2] RTOH[3]
A21 D19 B20 C19
O
TTL
Page 26
1.0 Product Description.
G56054-0, Rev 1.0
SONET/SDH 2.5Gbps Transport Terminating Transceiver
VSC9142.
Table 1.1
TSPCLK1
Hardware Signal Definitions (9 of 12)
Pad
A16
Pin Label
I/O
O
Type
TTL
Signal Name
Transmit Special Purpose Clock 1 Transmit Special Purpose Frame Pulse 1
Description
This is a clock reference for transmit special purpose port 1. The frequency is 2.16MHz with a 50% duty cycle (optionally gapped to match the bandwidth of TSPDAT1). This is a frame reference for transmit special purpose port 1. Mode 1 (TSPCLK1 continuous): TSPFP1 outputs a single-cyclewide pulse indicating the start of a new data stream on TSPDAT1. After TSPFP1 is asserted, the first bit of TSPDAT1 is sampled on the second rising edge of TSPCLK1. TSPFP1 transitions occur on the falling edge of TSPCLK1. Mode 2 (TSPCLK1 gapped): TSPFP1 outputs a single-cyclewide pulse (variable width due to the gapped clock) indicating the start of a new data stream on TSPDAT1. After TSPFP1 is asserted, the first bit of TSPDAT1 is sampled on the second rising edge of TSPCLK1. TSPFP1 transitions occur on the falling edge of TSPCLK1. This is a read enable for transmit special purpose port 1. TSPREN1 assertion to TSPDAT1 sampling is programmable. TSPREN1 transitions occur on TSPCLK1 falling edges. This is the serial data input for transmit special purpose port 1. TSPDAT1 is sampled on the rising edge of TSPCLK1. This is a clock reference for transmit special purpose port 2. The frequency is 2.16MHz with a 50% duty cycle (optionally gapped to match the bandwidth of TSPDAT2). This is a frame reference for transmit special purpose port 2. Mode 1 (TSPCLK2 continuous): TSPFP2 outputs a single-cyclewide pulse indicating the start of a new data stream on TSPDAT2. After TSPFP2 is asserted, the first bit of TSPDAT2 is sampled on the second rising edge of TSPCLK2. TSPFP2 transitions occur on the falling edge of TSPCLK2. Mode 2 (TSPCLK2 gapped): TSPFP2 outputs a single-cyclewide pulse (variable width due to the gapped clock) indicating the start of a new data stream on TSPDAT2. After TSPFP2 is asserted, the first bit of TSPDAT2 is sampled on the second rising edge of TSPCLK2. TSPFP2 transitions occur on the falling edge of TSPCLK2. This is a read enable for transmit special purpose port 2. TSPREN2 assertion to TSPDAT2 sampling is programmable. TSPREN2 transitions occur on TSPCLK2 falling edges. This is the serial data input for transmit special purpose port 2. TSPDAT2 is sampled on the rising edge of TSPCLK2. This is a clock reference for the transmit transport overhead port. The frequency is 38.88MHz with a 50% duty cycle. This is a frame reference for the transmit transport overhead port. TTOHFP outputs a single clock-cycle-wide pulse indicating the start of a new data stream on TTOH[3..0]. The time from TTOHFP assertion to sampling the first bit on TTOH[3..0] is programmable (see TTOHREN). TTOHFP transitions on a falling edge of TTOHCLK. This is a read enable for TTOH[3..0]. The time from TTOHREN assertion to TTOH[3..0] sampling is programmable. TTOHREN transitions occur on the falling edge of TTOHCLK.
TSPFP1
A13
O
TTL
Tx Overhead Transport Access Processor (TOAP) Signals
TSPREN1
B15
O
TTL
TSPDAT1 TSPCLK2
A15 B13
I O
TTL TTL
Transmit Special Purpose Read Enable 1 Transmit Special Purpose Data 1 Transmit Special Purpose Clock 2 Transmit Special Purpose Frame Pulse 2
TSPFP2
B12
O
TTL
TSPREN2
B11
O
TTL
TSPDAT2 TTOHCLK TTOHFP
D13 C13 C12
I O O
TTL TTL TTL
Transmit Special Purpose Read Enable 2 Transmit Special Purpose Data 2 Transmit Transport Overhead Clock Transmit Transport Overhead Frame Pulse
TTOHREN
A12
O
TTL
Transmit Transport Overhead Read Enable
4.0 Electrical & Mechanical Data
Page 27.
G56054, Rev 1.0
STS-48c Physical Layer Packet/ATM Over SONET/SDH Device
VSC9142
Table 1.1
Pin Label
TTOHEN
Hardware Signal Definitions (10 of 12)
Pad
C14
I/O
I
Type
TTL
Signal Name
Transmit Transport Overhead Enable
Description
When asserted, this signal enables insertion of TTOH[3..0] in the corresponding transport overhead octet of the outgoing STS-48 data stream. Transport overhead for the entire STS-48 is input as 4-bit nibbles on TTOH[3..0] (see TTOH[3..0] description). TTOHEN assertion during the first nibble of an overhead octet enables the corresponding overhead octet on TTOH[3..0]. Note: The Section and Line transmit overhead processing blocks (TSOP/TLOP) can selectively overwrite overhead octets inserted through the TTOH interface.
Tx Overhead Transport Access Processor (TOAP) Signals
TTOH[0] TTOH[1] TTOH[2] TTOH[3]
D16 C16 D15 C15
I
TTL
Transmit Transport Overhead Data
These are the data inputs for the transmit transport overhead (Section and Line) octets to be inserted in the outgoing STS-48 data stream. TTOH[3..0] carries the entire transport overhead in the order the octets are to be inserted. The most significant nibble (first received) is input first. TTOH[3] is the most significant bit. TTOH[3..0] is sampled on the rising edge of TTOHCLK.
D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8]
AB6 AC4 AD4 AB7 AC5 AC6 AD6 AC7 AB9 AD7 AA10 AC9 AD9 AC10 AB11 AC11 AB13
I/O
TTL
CPU Data
Microprocessor Interface Signals
This is a bidirectional data bus that provides microcontroller read/write access for transferring data to and from the device's internal registers.
I
TTL
CPU Address
This is the register address bus used to select specific internal registers during microcontroller read/write accesses.
Page 28
1.0 Product Description.
G56054-0, Rev 1.0
SONET/SDH 2.5Gbps Transport Terminating Transceiver
VSC9142.
Table 1.1
Pin Label
ALE
Hardware Signal Definitions (11 of 12)
Pad
AA12
I/O
I
Type
TTL
Signal Name
CPU Address Latch Enable
Description
This signal is used to latch internal address bus signals, enabling access to the device's multiplexed address/data bus. When low the address bus A[8..0] is latched internally. When high the internal address bus latches are transparent, which enables the bus to interface with multiplexed address/data. The ALE signal has an internal pull-up resistor. This signal must be asserted to enable internal register read/write access cycles (active low). The CSB signal is used in conjunction with the RDB/WRB signals. The CSB signal has an internal pullup resistor. This signal is used for internal register read operations. When RDB and CSB are both asserted (active low), data in the register selected by A[8..0] is presented at D[7..0]. The RDB signal has an internal pull-up resistor. This signal is used for internal register write operations. When WRB and CSB are both asserted (active low), data present at D[7..0] is written to the register selected by A[8..0]. The WRB signal has an internal pull-up resistor. This signal is asserted (active low) when an internal interrupt source is pending and the interrupt is unmasked (enabled). The INTB signal is de-asserted when the interrupt pending bits have been cleared. The INTB is an open-drain signal. This signal is used to perform an asynchronous reset of the device (active low). The device is held in a reset state while the RSTB signal is low. The signal is Schmitt-trigged with an internal pull-up resistor. All outputs are tristated when RSTB is asserted. This bidirectional signal pin provides a means of monitoring PM Ticks (performance monitoring ticks) and latching internal performance monitoring counters. Output: When configured as an output, this signal is optionally asserted when the internal PMTICK timer generates a "PM Tick", which latches the performance monitoring counters in the device. Input: A low-to-high transition optionally latches the performance monitoring counters in the device. Note: This pin is configured as an input on reset. These are general purpose pins that are individually-configurable as inputs or outputs. They are intended for user-customizable control and monitoring functions between the VSC9142 and external devices.
CSB
AD10
I
TTL
CPU Chip Select (active low)
RDB
AB8
I
TTL
CPU Read Enable (active low)
Microprocessor (CPU) Interface Signals
WRB
AB10
I
TTL
CPU Write Enable (active low)
INTB
AA9
O
TTL
CPU Interrupt (active low)
RSTB
AD3
I
TTL
Chip Reset (active low)
PMTICK
AB12
I/O
TTL
Performance Monitoring Tick
GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7]
AA20 AB20 AA19 AC20 AB19 AC19 AD19 AB18
I/O
TTL
General Purpose Input/Output
4.0 Electrical & Mechanical Data
Page 29.
G56054, Rev 1.0
STS-48c Physical Layer Packet/ATM Over SONET/SDH Device
VSC9142
Table 1.1
Pin Label
TDO
Hardware Signal Definitions (12 of 12)
Pad
AC21
I/O
O
Type
TTL
Signal Name
JTAG Test Data Output
Description
This signal carries test data out of the device via the IEEE P1149.1 test access port. TDO is updated on the falling edge of TCK. The TDO signal is a tristate output that is inactive except when data scan shifting is in progress. The signal carries test data into the device via the IEEE P1149.1 test access port. TDI is sampled on the rising edge of TCK. TDI has an internal pull-up resistor. This signal provides timing for test operations that are carried out using the IEEE P1149.1 test access port. This signal controls the test operations that are carried out using the IEEE P1149.1 test access port. TMS is sampled on the rising edge of TCK. TMS has an internal pull-up resistor. This signal is an asynchronous reset for the IEEE P1149.1 test access port (active low). TRSTB is a Schmitt-triggered input with an internal pull-up resistor. This signal is the test access port enable (active high). When deasserted (low), all TTL device outputs are tristated. OE has an internal pull-up resistor.
JTAG Test Access Port Signals
TDI
AD22
I
TTL
JTAG Test Data Input JTAG Test Clock JTAG Test Mode Select JTAG Test Reset
TCK TMS
AB21 AC22
I I
TTL TTL
TRSTB
AB24
I
TTL
OE
AD21
I
TTL
Chip Output Enable
Corporate Headquarters
Vitesse Semiconductor Corporation * 741 Calle Plano * Camarillo, CA 93012 Tel: 1-800-VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com www.vitesse.com
This document is an excerpt of the VSC9142 Data Book. For the complete data book, please contact your local sales representative (NDA required). Notice
Vitesse Semiconductor Corporation ("Vitesse") provides this document for informational purposes only. This document contains pre-production information about Vitesse products in their concept, development and/or testing phase. All information in this document, including descriptions of features, functions, performance, technical specifications and availability, is subject to change without notice at any time. Nothing contained in this document shall be construed as extending any warranty or promise, express or implied, that any Vitesse product will be available as described or will be suitable for or will accomplish any particular task. Vitesse products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is prohibited.
Page 30
1.0 Product Description.

▲Up To Search▲

Price & Availability of VSC9142

	To Download VSC9142 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .